Digital circuits
This module presents the basic concepts of MOSFET digital logic circuits. We will examine NMOS logic circuits, which contain only n-channel transistors, and complementary MOS, or CMOS, logic circuits, which contain both n-channel and p-channel ...
This module presents the basic concepts of MOSFET digital logic circuits. We will examine NMOS logic circuits, which contain only n-channel transistors, and complementary MOS, or CMOS, logic circuits, which contain both n-channel and p-channel transistors. JFET logic circuits are very specialized and therefore not considered here.
The NMOS inverter is the basic of NMOS digital logic circuits. We will analyze the dc voltage transfer characteristics of several inverter designs. We will also define and develop the noise margin of NMOS digital circuits in terms of the inverter voltage transfer curve. We will then determine the impact of the body effect on the dc voltage transfer curve and the logic levels. A transient analysis of the NMOS inverter will determine the propagation delay time in NMOS logic circuits. We will then develop and analyze basic NMOS NOR and NAND logic gates, as well as circuits that perform more complex logic functions.
The CMOS inverter is the basic of CMOS logic gates. We will analyze the inverter dc voltage transfer characteristics, and will determine the power dissipation in the CMOS inverter, demonstrating the principle advantage of CMOS inverter over NMOS circuits. Next, we will develop the noise margin of the CMOS inverter, and then will develop and analyze basic CMOS NOR and NAND logic gates. Finally, we will look at more advanced clocked CMOS logic circuits which eliminate almost half of transistors in a conventional CMOS logic design while maintaining the low power advantage of the CMOS technology.
In a digital system, a transistor can act as a switch between a driving circuit and a load circuit. An NMOS transistor that performs this function is called an NMOS transmission gate; the corresponding CMOS configuration is a CMOS transmission gate. These transmission gates, or pass transistors, can also be configured to perform logic functions, and the circuits are called NMOS-pass or CMOS-pass networks. We will discuss the basics of these networks.
Finally in this module, we will consider a few examples of sequential logic circuits. Two dynamic shift registers are defined and analyzed, and a static R-S flip-flop are defined and analyzed.
The inverter is the basic circuit of most MOS logic circuits. The design techniques used in NMOS logic circuits are developed from the dc analysis results for NMOS inverter. Extending the concepts developed from the inverter to NOR and NAND gates is then direct. Alternative inverter load elements are compared in terms of power consumption, packing density, and transfer characteristics. The transient analysis and switching characteristics of the inverters give an indication of the propagation delay times of NMOS logic circuits.
n-Channel MOSFET
In this section, we will quickly review the n-channel MOSFET characteristics, emphasizing specific properties important in digital circuit design.
A simplified n-channel MOSFET is shown in [link]. The body or substrate, is a single crystal silicon wafer which is the starting material for circuit fabrication and provides physical support for the integrated circuit. The active transistor region is the surface of the semiconductor and is comprised of the heavy doped n+ size 12{n rSup { size 8{+{}} } } {} source and drain regions and p-type channel region. The channel length is L and the channel awidth is W. normally, in any given fabrication process, the channel length is the same for all transistors, while the channel awidth is variable.
a) n-chanel MOSFET simplified view and b)n-channel MOSFET detailed cross section
[link]b shows a more detailed view of the n-channel MOSFET. This figure demonstrates that the actual device geometry is more complicated than that indicated by the simplified cross section.
a) Simplified circuit symbols for n-channel MOSFETs and b) circuit symbols showing substrate or body terminal
[link]a shows the simplified circuit symbols for the n-channel enhancement and depletion-mode devices. When we explicitly consider the body or substrate connection, we will use the symbols shows in [link]b.
In an integrated circuit, all n-channel transistors are fabricated in the same p-type substrate material. The substrate is connected to the most negative potential in the circuit, which for digital circuits, is normally at ground potential or zero volts. However, the source terminal of many of transistors will not be at zero volts, which means that a reverse-biased pn junction will exist between source and substrate.
When the source and body terminal are connected together, the threshold voltage, to a first approximation, is independent of the applied voltages. However, when the source and body voltages are not equal, as when transistors are used for active loads, for instance, the threshold voltage is a function of difference between these voltages. We can write
where VSB size 12{V rSub { size 8{ ital "SB"} } } {} is the source-to-body voltage, and VTh0 size 12{V rSub { size 8{ ital "Th"0} } } {} is the threshold voltage for zero source-to-body voltage or VSB=0 size 12{V rSub { size 8{ ital "SB"} } =0} {}. The parameter Na size 12{N rSub { size 8{a} } } {} is the p-type substrate doping concentration, εs size 12{ε rSub { size 8{s} } } {} is the semiconductor permittivity, Cox size 12{C rSub { size 8{ ital "ox"} } } {} is the oxide capacitance per unit area, φfp size 12{φ rSub { size 8{ ital "fp"} } } {} is a potential related to the substrate doping concentration, and γ size 12{γ} {} is the body-effect coefficient.
The current-voltage characteristics of the n-channel MOSFET are functions of both the electrical and geometrical properties of the device. When the transistor is biased in the nonsaturation region, for vGS≥VTh size 12{v rSub { size 8{ ital "GS"} } >= V rSub { size 8{ ital "Th"} } } {} and vDS≤(vGS−VTh) size 12{v rSub { size 8{ ital "DS"} } <= ( v rSub { size 8{ ital "GS"} } - V rSub { size 8{ ital "Th"} } ) } {}, we can write
In the saturation region, for vGS≥VTh size 12{v rSub { size 8{ ital "GS"} } >= V rSub { size 8{ ital "Th"} } } {}, and vDS≥(vGS−VTh) size 12{v rSub { size 8{ ital "DS"} } >= ( v rSub { size 8{ ital "GS"} } - V rSub { size 8{ ital "Th"} } ) } {}, we have
The transition point separates the non-saturation and saturation regions and is the drain-to-source saturation voltage which is given by
The term (1+λvDS) size 12{ ( 1+λv rSub { size 8{ ital "DS"} } ) } {} is sometimes included in [link]b to account for channel length modulation and the finite output resistance. In most cases, it has little effect on the operating characteristics of MOS digital circuits. In our analysis, the term λ size 12{λ} {} is assumed to be zero unless otherwise stated.
The parameter kn size 12{k rSub { size 8{n} } } {} is the NMOS transistor conduction parameter and is given by
The electron mobility μn size 12{μ rSub { size 8{n} } } {} and oxide capacitance C0x size 12{C rSub { size 8{0x} } } {} are assumed to be constant for all devices in a particular IC.
The current-voltage characteristics are directly related to the channel awidth-to-length ratio, or the size of the transistor. In general, in a given IC, the length L is fixed, but the designer can control the channel awidth W.
Since the MOS transistor is a majority carrier device, the switching speed of MOS digital circuits is limited by the time required to charge or discharge the capacitances between device electrodes and between interconnect lines and ground. [link] shows the significant capacitances in a MOSFET. The capacitances Csb size 12{C rSub { size 8{ ital "sb"} } } {} and Cdb size 12{C rSub { size 8{ ital "db"} } } {} are the source-to-body and drain-to-body n+ size 12{n rSup { size 8{+{}} } } {}p junction capacitances. The total input gate capacitance, to a first approximation, is a constant equal to
where C0x size 12{C rSub { size 8{0x} } } {} is the oxide capacitance per unit area, and is a function of the oxide thickness. The parameter C0x size 12{C rSub { size 8{0x} } } {} also appears in the expression for the conduction parameter.
n-channel MOSFET and device capacitances
NMOS Inverter Transfer Characteristics
Since the inverter is the basic for most logic circuits, we will describe the NMOS inverter and will develop the dc transfer characteristics for three types of inverters with different load devices. This discussion will introduce voltage transfer functions, noise margins, and the transient characteristics of FET digital circuits.
NMOS inverter with resistor load
[link]a shows a single NMOS transistor connected to a resistor to form an inverter. The transistor characteristics and load line are shown in [link]b, along with the parametric curve separating the saturation and nonsaturation regions. We determine the voltage transfer characteristics of the inverter by examining the various regions in which the transistor can be biased.
a) NMOS inverter with resistor load and b) transistor characteristics and load line
When the input voltage is less than or equal to the threshold, or vI≤VTh size 12{v rSub { size 8{I} } <= V rSub { size 8{ ital "Th"} } } {}, the transistor is cut off, iD=0 size 12{i rSub { size 8{D} } =0} {}, and the output voltage is v0=VDD size 12{v rSub { size 8{0} } =V rSub { size 8{ ital "DD"} } } {}. The maximum output voltage is defined as the logic 1 level. As the input voltage becomes just greater than VTh size 12{V rSub { size 8{ ital "Th"} } } {}, the transistor turns on and is biased in the saturation region. The output voltage is than
Where the drain current is given by
Combining [link] and [link] yields
which relates the output and input voltages as long as the transistor is biased in the saturation region.
As the input voltage increases, the Q-point of the transistor moves up the load line. At the transition point, we have
where V0t size 12{V rSub { size 8{0t} } } {} and VIt size 12{V rSub { size 8{ ital "It"} } } {} are the drain-to-source and gate-to-source voltage, respectively, at the transition point. Substituting [link] into [link], the input voltage at the transition point is the determined from
As the input voltage becomes greater than VIt size 12{V rSub { size 8{ ital "It"} } } {}, the Q-point continues to move up the load line, and the transistor becomes biased in the nonsaturation region. The drain current is then
Combining [link] and [link] yields
Which relates to the input and output voltage as long as the transistor is biased in the nonsaturation region.
[link] shows the voltage transfer characteristics of this inverter for three resistor values. Also shown is the line, given by [link], which separates the saturation and nonsaturation bias region of the transistor. The figure shows that the minimum output voltage, or the logic 0 level, for a high input decreases with increasing load resistance, and the sharpness of the transition region between a low input and a high input increases with increasing load resistance.
Voltage transfer characteristics, NMOS inverter with resistor load, for three resistor values
It should be note that a large resistance is difficult to fabricate in an IC. A large resistor value in the inverter will limit current and power consumption as well as provide a small VOL size 12{V rSub { size 8{ ital "OL"} } } {} value. But it would also require a large chip area if fabricated in a standard MOS process. To avoid this problem, MOS transistors can be used as load devices, replacing the resistor, as discussed in subsequent paragraphs.
NMOS inverter with enhancement load
An n-channel enhancement-mode MOSFET with the gate connected to the drain can be used as a load device in an NMOS inverter. [link]a shows such a device. For vGS=vDS≤VTh size 12{v rSub { size 8{ ital "GS"} } =v rSub { size 8{ ital "DS"} } <= V rSub { size 8{ ital "Th"} } } {}, the drain current is zero. For vGS=vDS≥VTh size 12{v rSub { size 8{ ital "GS"} } =v rSub { size 8{ ital "DS"} } >= V rSub { size 8{ ital "Th"} } } {}, a nonzero drain current is induced in the device. We can see that the following condition is satisfied:
A transistor with this connection always operates in the saturation region when not in cutoff.
The drain current is
We continue to neglect the effect of the output resistance and the λ size 12{λ} {} parameter. The iD size 12{i rSub { size 8{D} } } {} versus vDC size 12{v rSub { size 8{ ital "DC"} } } {} characteristic is shown in [link]b which indicates that this device acts as a nonlinear resistor.
a) n-channel MOSFET connected as saturated load device and b) current-voltage characteristics of saturated load device
[link]a shows an NMOS inverter with the enhancement load device. The driver transistor parameters are denoted by VThL size 12{V rSub { size 8{ ital "ThL"} } } {} and kL size 12{k rSub { size 8{L} } } {}. The substrate connections are not shown. In the following analysis, we neglect the body effect and we assume all threshold voltages are constant. These assumptions do not seriously affect the basic analysis or the inverter characteristics.
The driver transistor characteristics and the load curve are shown in [link]b. When the inverter input voltage is less than the driver threshold voltage, the driver is cut off and the drain currents are zero. From [link], we have
From [link]a, we see that vDSL=VDD−v0 size 12{v rSub { size 8{ ital "DSL"} } =V rSub { size 8{ ital "DD"} } - v rSub { size 8{0} } } {}, which means that
The maximum output voltage is then
For the enhancement load NMOS inverter, the maximum output voltage, which is the logic 1 level, does not reach the full VDD size 12{V rSub { size 8{ ital "DD"} } } {} value. This cutoff point is shown on the load curve in [link]b.
a) NMOS inverter with saturated load and b) driver transistor characteristics and load curve
As the input voltage becomes just greater than the driver threshold voltage VThD size 12{V rSub { size 8{ ital "ThD"} } } {}, the driver transistor turns on and is biased in the saturation region. In steady-state, the two drain currents are equal since the output will be connected to the gates of other MOS transistors. We have iDD=iDL size 12{i rSub { size 8{ ital "DD"} } =i rSub { size 8{ ital "DL"} } } {}, which can be written as
[link] is expressed in terms of the individual transistor parameters. In terms of the input and output voltages, the expression becomes
Solving for the output voltage yields
As the input voltage increases, the driver Q-point moves up the load curve and the output voltage deceases linearly with vI size 12{v rSub { size 8{I} } } {}.
At the driver transition point, we have
v DSD ( sat ) = v GSD − V ThD size 12{v rSub { size 8{ ital "DSD"} } ( ital "sat" ) =v rSub { size 8{ ital "GSD"} } - V rSub { size 8{ ital "ThD"} } } {}
or
Substituting [link] into [link], we find the input voltage at the transition point, which is
As the input voltage becomes greater than VIt size 12{V rSub { size 8{ ital "It"} } } {}, the driver transistor Q-point continues to move up the load curve and the driver becomes biased in the nonsaturation region. Since the driver and load drain currents are still equal, or iDD=iDL size 12{i rSub { size 8{ ital "DD"} } =i rSub { size 8{ ital "DL"} } } {}, we now have
Writing [link] in terms of the input and output voltages produces
Obviously, the relationship between v1 size 12{v rSub { size 8{1} } } {} and v0 size 12{v rSub { size 8{0} } } {} in this region is not linear.
[link] shows the voltage transfer characteristics of this inverter for three kD size 12{k rSub { size 8{D} } } {}-to- kL size 12{k rSub { size 8{L} } } {} ratios. The ratio kD/kL size 12{ {k rSub { size 8{D} } } slash {k rSub { size 8{L} } } } {} is the aspect ratio and is related to the awidth-to-length parameters of the driver and load transistors.
The line, given by [link], separating the driver saturation and nonsaturation regions is also shown in the figure. We see that the minimum output voltage, or the logic 0 level, for a high input decreases with an increasing kD/kL size 12{ {k rSub { size 8{D} } } slash {k rSub { size 8{L} } } } {} ratio. As the awidth-to-length ratio of the load transistor decreases, the effective resistance increases, which means that the general behavior of the transfer characteristics is the same as for the resistor load. However, the high output voltage is
V OH = V DD − V ThL size 12{V rSub { size 8{ ital "OH"} } =V rSub { size 8{ ital "DD"} } - V rSub { size 8{ ital "ThL"} } } {}
When the driver is biased in the saturation region, we find the slope of the transfer curve, which is the inverter gain, by taking the derivative of [link] with respect to vI size 12{v rSub { size 8{I} } } {}. We see that
dv 0 / dv I = − k D / k L size 12{ ital "dv" rSub { size 8{0} } / ital "dv" rSub { size 8{I} } = - sqrt {k rSub { size 8{D} } /k rSub { size 8{L} } } } {}
When the aspect ratio is greater than unity, the inverter gain magnitude is greater than unity. A logic circuit family with an inverter transfer curve that exhibits a gain greater than unity for some region is called a restoring logic family. Restoring logic is so named because logic signals that are degraded for some reason in one circuit can be restored by gain of subsequent logic circuits.
Voltage transfer characteristics, NMOS inverter with saturated load, for three aspect ratios
NMOS inverter with depletion load
Depletion mode MOSFET can also be used as load elements in NMOS inverters. [link]a shows the NMOS inverter with depletion load. The gate and source of the depletion mode transistor are connected together. The driver transistor is still an enhancement-mode device. As before, the driver transistor parameters are VThD size 12{V rSub { size 8{ ital "ThD"} } } {} ( VThD size 12{V rSub { size 8{ ital "ThD"} } } {}> 0) and kD size 12{k rSub { size 8{D} } } {}, and the load transistor parameters are VThL size 12{V rSub { size 8{ ital "ThL"} } } {} ( VThL size 12{V rSub { size 8{ ital "ThL"} } } {}< 0) and kL size 12{k rSub { size 8{L} } } {}. Again, the substrate connections are not shown. The fabrication process for this inverter is slightly more complicated than for the enhancement-load inverter, since the threshold voltages of the two devices are not equal. However, as we will see, the advantage of the inverter makes the extra processing steps worthwhile. This inverter has been the basic of many microprocessor and static memory designs.
a) NMOS inverter with depletion load, b) current-voltage characteristic of depletion load, and c) driver transistor characteristics and load curve
The current-voltage characteristic curve for the depletion load, neglecting the body effect, is shown in [link]b. Since the gate is connected to the source, vGSL=0 size 12{v rSub { size 8{ ital "GSL"} } =0} {}, and the Q-point of the load is on this particular curve.
The driver transistor characteristics and the ideal load curve are shown in [link]c. When the inverter input is less than the driver threshold voltage, the driver is cut off and the drain currents are zero. From [link]b, we see that for vD=0 size 12{v rSub { size 8{D} } =0} {}, the drain-to-source voltage of the load transistor must be zero; therefore, v0=VDD size 12{v rSub { size 8{0} } =V rSub { size 8{ ital "DD"} } } {} for vI≤VThD size 12{v rSub { size 8{I} } <= V rSub { size 8{ ital "ThD"} } } {}. An advantage of the depletion load inverter over the enhancement-load inverter is that the high output voltage, or the logic 1 level, is at the full VDD size 12{V rSub { size 8{ ital "DD"} } } {} value.
As the input voltage becomes just greater than the driver threshold voltage VThD size 12{V rSub { size 8{ ital "ThD"} } } {}, the driver turns on and is biased in the saturation region; however, the load is biased in the nonsaturation region. The Q-point lies between points A and B on the load curve shown in Figure 9c. We again set the two drain currents equal, or iDD=iDL size 12{i rSub { size 8{ ital "DD"} } =i rSub { size 8{ ital "DL"} } } {}, which means that
Writing [link] in terms of the input and output voltages yields
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